Package-on-package (PoP) stacking of substrates and devices offers significant advantages primarily related to reducing device footprint. PoP is used to improve electrical performance due to shortened interconnections between associated packages. PoP can also be used to improve testability by, for example, permitting separate testing of logic and memory devices.
In advanced substrate level packaging, PoP is used to save area by stacking different dies and different functionality packages atop each other. However, PoP technology still has problems posed by the inherent conflict between the need to minimize thickness and the need to minimize and withstand warpage. Warpage creates some of the most debilitating problems encountered in PoP assemblies, such as open or short circuits caused by the separation of materials, or by the ingress of moisture between separated materials. Thin PoP assemblies having layers of different thermal properties are particularly affected by warping. Several common PoP processing are used to address these problems. However, the inventors have observed that the commonly available PoP processes are ineffective, costly, and time consuming.
Accordingly, the inventors have developed improved techniques for forming PoP assembly packages having larger effective die surface area, robust package-to-package connectivity, and reduced warpage.